(a) Field of the Invention
The present invention relates to a method of fabricating a transistor in a semiconductor device.
(b) Discussion of the Related Art
It is known to provide a junction structure during manufacture of a semiconductor device by one-step implantation. A lightly doped drain (LDD) junction structure has been proposed to reduce undesirable effects caused by reduced gate lengths.
In order to provide the LDD junction structure, two-step implantation is employed using a gate sidewall spacer. In the two-step implantation, a gate is formed by performing photolithography on polysilicon and oxide formed on a silicon substrate. Light source/drain implantation is then performed on the silicon substrate. Specifically, oxidation is performed to protect the silicon substrate and to restore an edge portion of the gate oxide layer prior to the source/drain implantation.
After completion of the light source/drain implantation, a gate sidewall spacer is formed by stacking an oxide layer and silicon nitride layer over the silicon substrate. Etching back of the stacked layers and heavy source/drain implantation are performed on the substrate to complete the junction.
During the process, the gate sidewall spacer is used as a barrier for preventing a silicide bridge between an active area (AA) and a gate polysilicon conductor from occurring in silicidation.
FIGS. 1A to 1I are cross-sectional diagrams showing a related art method of fabricating a transistor in a semiconductor device.
As shown in FIG. 1A, an oxide layer is formed on a silicon substrate 100, and a polysilicon layer is formed on the oxide layer. Photolithography is performed on the polysilicon layer and the oxide layer to form a gate oxide layer 101 and a gate 102.
As shown in FIG. 1B, an oxide layer 103 is formed on the silicon substrate 100 including exposed surfaces of the gate oxide layer 101 and the gate 102 by oxidation to restore edges of the gate oxide layer 101 and to protect the silicon substrate 100.
As shown in FIG. 1C, light ion implantation is performed on the silicon substrate 100 to lightly doped regions 104. An oxide layer 105 and a silicon nitride layer 106 are stacked over the substrate 100, as shown in FIG. 1D.
As shown in FIG. 1E, the oxide layer 105 and the silicon nitride layer 106 are etched back to remain on a sidewall of the gate 102 and the gate oxide layer 101. By this process, a gate sidewall spacer 106/105 is formed.
As shown in FIG. 1F, heavy ion implantation is performed on the silicon substrate 100 to form heavily doped regions 107 adjacent to the lightly doped regions 104, respectively. Silicidation is performed on the gate 102 and the heavily doped regions 107 to form a silicide layer 108, as shown in FIG. 1G.
As shown in FIG. 1H, a premetal dielectric (PMD) layer 109 is formed on the silicon substrate 100 including the silicide layer 108. FIG. 1I shows an insulating interlayer 110 formed on the PMD layer 109. However, since a space between the gates is narrowed due to the gate sidewall spacer 106/105 and the PMD layer 109, a void V1 is formed while depositing the insulating interlayer 110.
The void V1 can generate cracks or bridges in subsequent thermal and contact processes, thus lowering the yield and reliability of the semiconductor device.